DSPIC30F4011-30I/ML【PDF 17/238 页】IC DSPIC MCU/DSP 48K 44QFN

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Sheet目录1917

13页 14页 15页 16页 [17页]18页 19页 20页 21页

2010 Microchip Technology Inc.

DS70135G-page 113

dsPIC30F4011/4012

17.0

I2C MODULE

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard with a 16-bit interface.

This module offers the following key features:

I2C Interface supporting both Master and Slave

Operation

I2C Slave mode supports 7-bit and 10-bit address-

ing

I2C Master mode supports 7-bit and 10-bit

addressing

I2C Port allows Bidirectional Transfers between

Master and Slaves

Serial Clock Synchronization for I2C Port can be

used as a Handshake Mechanism to Suspend

and Resume Serial Transfer (SCLREL control)

I2C supports Multi-Master Operation; detects bus

collision and will arbitrate accordingly

17.1

Operating Function Description

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

Thus, the I2C module can operate either as a slave or

a master on an I2C bus.

17.1.1

VARIOUS I2C MODES

The following types of I2C operation are supported:

I2C slave operation with 7-bit addressing

I2C slave operation with 10-bit addressing

I2C master operation with 7-bit or 10-bit addressing

See the I2C programmer’s model in Figure 17-1.

17.1.2

PIN CONFIGURATION IN I2C MODE

I2C has a 2-pin interface. The SCL pin is clock and the

SDA pin is data.

17.1.3

I2C REGISTERS

I2CCON and I2CSTAT are control and status registers,

respectively. The I2CCON register is readable and writ-

able. The lower 6 bits of I2CSTAT are read-only. The

remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written or from which data bytes are read.

I2CRCV is the receive buffer, as shown in Figure 17-1.

I2CTRN is the transmit register to which bytes are

written during a transmit operation, as shown in

Figure 17-2.

The I2CADD register holds the slave address. A status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator reload

value.

In receive operations, I2CRSR and I2CRCV together

form a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and

interrupt

pulse

generated.

During

transmission, the I2CTRN is not double-buffered.

FIGURE 17-1:

PROGRAMMER’S MODEL

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals,

descriptions

and

general device functionality, refer to the

dsPIC30F

Family

Reference

Manual

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Reference Manual” (DS70157).

Note:

Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit address.

bit 7

bit 0

I2CRCV (8 bits)

bit 7

bit 0

I2CTRN (8 bits)

bit 8

bit 0

I2CBRG (9 bits)

bit 15

bit 0

I2CCON (16-bits)

bit 15

bit 0

I2CSTAT (16-bits)

bit 9

bit 0

I2CADD (10-bits)

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